10.7 An 11GHz 2nd-order DPD FMCW chirp generator with 0.051% rms frequency error under a 2.3GHz chirp bandwidth, 2.3GHz/μs slope, and 50ns idle time in 65nm CMOS - Télécom SudParis
Communication Dans Un Congrès Année : 2024

10.7 An 11GHz 2nd-order DPD FMCW chirp generator with 0.051% rms frequency error under a 2.3GHz chirp bandwidth, 2.3GHz/μs slope, and 50ns idle time in 65nm CMOS

Résumé

A frequency-modulated continuous-wave (FMCW) chirp generator serves as the pivotal building block for short-range 3D imaging radar systems, which have been widely utilized in medical and security applications. To enable quick and precise scanning with sub-millisecond snapshot duration and sub-centimeter depth resolution in a 79GHz large-scale MIMO radar imaging system, which composes of hundreds of TX/RX elements, the FMCW chirp generator must generate chirps with about 1μs chirp duration and operate >15 GHz bandwidth (BW), necessitating an ultra-fast chirp slope exceeding 15GHz/μs. Meanwhile, high chirp linearity and low phase noise (PN) are also essential to improve the signal-to-noise ratio (SNR) for high-quality imaging, and the between-chirp idle time (Tidle) must be shortened to 50ns given that at least 95% of the chirp duty-cycle is required. To resolve the contradictions between narrow PLL BW for low PN and quick loop response for fast chirp, two-point-modulation (TPM) technique is widely implemented in fractional-N PLLs [1–5]. Regarding the linearity of an ultra-fast wideband chirp, it is challenging to effectively compensate for the residual frequency error (Ferror) of a 1st-order digital pre-distortion (DPD) [2–4] and the ramp non-linearity of a ramp tracker [1, 5] with an insufficient PLL bandwidth, calling for advanced curve fitting techniques. In this work, to diminish rms Ferror in the context of ultra-fast wideband chirp generation, a ramp-tracker assisted 2nd-order curve-fitting (2nd-CF) DPD is proposed in a fractional-N sub-sampling (SS) PLL, achieving an 11GHz fast saw-tooth chirp with a 2.3GHz chirp bandwidth, 2.3GHz/μs chirp slope, and 0.051% rms Ferror. Leveraging an integral path in the digital loop filter (DLF), dynamic track-and-hold functionalities are realized in the voltage tracking loop (VTL) for robust LUT calibration. Advanced phase control is inve...
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hal-04870066 , version 1 (07-01-2025)

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Xuan Wang, Xujun Ma, Yupeng Fu, Yuqian Zhou, Ang Li, et al.. 10.7 An 11GHz 2nd-order DPD FMCW chirp generator with 0.051% rms frequency error under a 2.3GHz chirp bandwidth, 2.3GHz/μs slope, and 50ns idle time in 65nm CMOS. 2024 IEEE International Solid-State Circuits Conference (ISSCC), Feb 2024, San Francisco, United States. pp.200-202, ⟨10.1109/ISSCC49657.2024.10454283⟩. ⟨hal-04870066⟩
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